
MPC8308_RDB Board Configuration
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
LBCM
DDRCM
SVCOD
SPMF
—
COREPLL
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
—
Figure 25. Reset Configuration Word Low Register (RCWLR)
0
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
Field
—
—
—
—
COREDIS BMS BOOTSEQ SWEN
ROMLOC
RLEXT
—
16
17
18
19
20
21
22
23
24
25 26 27
28
29
30
31
Field
TSEC1M
TSEC2M
—
TLE
—
Figure 26. Reset Configuration Word High Register (RCWHR)
Table 8. RCWLR Bit Descriptions
Bits
Name
Meaning
Description
0
LBCM
Local bus clock mode Local Bus Controller Clock: CSB_CLK
0 (Default)
ratio 1:1
1
ratio 2:1
1
2–3
DDRCM
SVCOD
DDR SDRAM clock
mode
System PLL VCO
division
DDR Controller Clock: CSB_CLK
0
ratio 1:1
1 (Default)
ratio 2:1
VCO Division Factor
00 (Default)
2
01
4
10
8
11
1
4–7
SPMF[0–3]
System PLL
multiplication factor
0000
0001
Reserved
Reserved
0010
0011
0100 (Default)
0101
0110
0111-1111
2:1
3:1
4:1
5:1
6:1
Reserved
8
—
Reserved
Must be cleared.
PowerQUICC? MPC8308_RDB User’s Guide, Rev. 3
Micetek International Inc.
27